FIG. 1 illustrates a prior art phase-locked loop (PLL) 100. PLL 100 includes a phase detector circuit 101, a loop filter circuit 102, an oscillator circuit 103, and a frequency divider circuit 104. Phase detector circuit 101 compares the phase of a feedback clock signal FBCLK to the phase of a reference clock signal REFCLK to generate a control signal VC. Loop filter circuit 102 filters control signal VC to generate a filtered control signal VCF. Oscillator circuit 103 generates a periodic output clock signal OUTCLK. Oscillator circuit 103 varies the frequency of OUTCLK based on changes in the filtered control signal VCF.
Frequency divider circuit 104 generates FBCLK in response to OUTCLK. Frequency divider circuit 104 divides the frequency of OUTCLK to generate the frequency of FBCLK. PLL 100 drives the phase difference and the frequency difference between FBCLK and REFCLK to zero.
Frequency divider circuit 104 typically consumes a substantial amount of power in order to generate the feedback clock signal FBCLK in response to a high frequency output clock signal OUTCLK. Frequency divider circuit 104 also generates jitter in OUTCLK. Therefore, it would be desirable to provide a phase-locked loop that generates a high frequency periodic output signal without requiring a frequency divider circuit that consumes a substantial amount of power and that generates jitter.